Where is RISC-V Summit Europe 2026 held?

RISC-V Summit Europe 2026 was held at Bologna Congress Center in Bologna, Italy.

Who is speaking at RISC-V Summit Europe 2026?

ConferenceGrid lists 32 speakers, including Adeel Ahmad, Anne Merlande and Bohua Kou.

Who sponsors RISC-V Summit Europe 2026?

ConferenceGrid lists 44 sponsors, including Beijing Institute of Open Source Chip, E4 Computing, MIPS, Nuclei System and Breker Systems.

Open Source

RISC-V Summit Europe 2026

Name: RISC-V Summit Europe 2026
Start: 2026-06-08
End: 2026-06-12
Location: Bologna Congress Center

This edition has ended

RISC-V Summit Europe 2026 ran Jun 8–12, 2026 at Bologna Congress Center in Bologna, Italy. It is an Open Source conference. ConferenceGrid lists 32 speakers, 44 sponsors and 25 sessions. Dates for the next edition are not announced yet.

Lineup updated Jun 16, 2026 · dates verified May 4, 2026

RISC-V Summit Europe 2026 will be held in Bologna, Italy, from June 8 to June 12. This event brings together the European RISC-V community to discuss the latest developments and innovations in open hardware, promoting collaboration and the advancement of the RISC-V ecosystem. The summit includes technical sessions, a developers' workshop, and opportunities f…

Visit the official site

32Speakers

44Sponsors

25Sessions

44Companies · in total

Speakers

Programmed at RISC-V, in alphabetical order.

Adeel Ahmad

Anne Merlande

Bohua Kou

Dave Cremins

Dr. Philipp Tomsich

Elisabetta Boella

Fengxue Zhang

Flavia Guella

Frédéric Pétrot

Gabriele Ceccolini

Guodong Xu

Haoyuan Liu

Iacopo Colonnelli

Johannes Sanwald

Jon Taylor

Luca Lingardo

Manuel Rodríguez

Michele Magno

Nathan Egge

Ottavio Monticelli

Prachi Pandey

PRANOSE J EDAVOOR

Agenda

Selected from 25 sessions.

TBA
Accelerating RISC-V Innovation with open MPACT Tools from Google
The MPACT Tools portfolio provides open-source tools that increase the velocity of HW-SW co-design and development of RISC-V based systems. MPACT-Sim [1] is an ISS framework in C++…
TBA
Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions
Computational Fluid Dynamics (CFD) relies heavily on the efficiency of linear solvers based on sparse linear algebra kernels. Widely used frameworks like OpenFOAM exploit paralleli…
TBA
All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom
RISC-V’s Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field λ. This yi…
TBA
An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs
Driven by the need for zonal control architectures in software-defined vehicles, open-source RISC-V cores are becoming a compelling solution for automotive microprocessor units (MP…
TBA
A Proof-of-Concept RISC-V with 128-bit Extension
Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a…
TBA
ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V
Modern data-centric workloads increasingly expose the limitations of traditional von Neumann architectures, where excessive data movement limits throughput and energy efficiency. W…
TBA
A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt
We present Bianbu LXQt, a user-oriented desktop environment for RISC-V platforms built on a deeply adapted LXQt software stack, optimized for real hardware such as SpacemiT’s K1 an…
TBA
Building the software ecosystem for a RISC-V datacenter
The RISC-V software ecosystem has grown steadily over the last few years. For embedded software it is reasonably complete, with good compiler, RTOS, and IDE support. The Linux kern…
TBA
CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures
The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing U…

Quick answers

When is RISC-V Summit Europe 2026?: RISC-V Summit Europe 2026 ran Jun 8–12, 2026 at Bologna Congress Center in Bologna, Italy.
Where is RISC-V Summit Europe 2026 held?: RISC-V Summit Europe 2026 was held at Bologna Congress Center in Bologna, Italy.
Who is speaking at RISC-V Summit Europe 2026?: ConferenceGrid lists 32 speakers, including Adeel Ahmad, Anne Merlande and Bohua Kou.
Who sponsors RISC-V Summit Europe 2026?: ConferenceGrid lists 44 sponsors, including Beijing Institute of Open Source Chip, E4 Computing, MIPS, Nuclei System and Breker Systems.

Company intelligence

An audience of 44 companies, parsed from the program.

44 companies in attendance.

The numbers below are derived from the speakers, sponsors, and exhibitors on this page, cross-referenced into one ledger. They are the only thing here that 10times.com cannot tell you.

Who's in the room

0All threespeak · spons · exh

44Sponsoringsponsor only

0Speakingspeaker only

Speakers by seniority

Other roles32100%

Of 32 speakers · classified by free-text title

Most-represented companies

#	Company	Roles	Speakers
1	Akeana	Sponsor · Silver	-
2	Andes	Sponsor · Silver	-
3	Arteris	Sponsor · Silver	-
4	Axelera	Sponsor · Silver	-
5	Barcelona Supercomputing Center (BSC-CNS)	Sponsor · Silver	-
6	Baya Systems	Sponsor · Silver	-
7	Beijing Institute of Open Source Chip	Sponsor · Platinum	-
8	Breker Systems	Sponsor · Gold	-
9	CEA	Sponsor · Gold	-
10	Chips-IT	Sponsor · Silver	-
11	CircuitSutra	Sponsor · Silver	-
12	DeepComputing	Sponsor · Silver	-
13	E4 Computing	Sponsor · Platinum	-
14	EE Times	Sponsor · Media Partner	-

Sponsors by tier

platinum4

9% of 44

gold10

23% of 44

silver27

61% of 44

bronze1

2% of 44

media partner2

5% of 44

RISC-V Summit Europe 2026

Accelerating RISC-V Innovation with open MPACT Tools from Google

Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions

All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom

An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs

A Proof-of-Concept RISC-V with 128-bit Extension

ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V

A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt

Building the software ecosystem for a RISC-V datacenter

CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures

44 companies in attendance.