GConferenceGridThe Conference Catalogue · Vol. 2026Folio № 716987
Of the Field

RISC-V Summit Europe 2026

R

ISC-V Summit Europe 2026 will be held in Bologna, Italy, from June 8 to June 12. This event brings together the European RISC-V community to discuss the latest developments and innovations in open hardware, promoting collaboration and the advancement of the RISC-V ecosystem. The summit includes technical sessions, a developers' workshop, and opportunities f…

Visit the official site
0Voices
44Underwriters
0Exhibitors
25On the bill · sessions
44Companies · in total
§II

Underwritten By

The houses behind the program. Tiers as disclosed.
Beijing Institute of Open Source ChipPlatinum
E4 ComputingPlatinum
MIPSPlatinum
Nuclei SystemPlatinum
Breker SystemsGold
CEAGold
Epic SemiGold
ESWIN ComputingGold
NextSiliconGold
QualcommGold
SiFiveGold
TenstorrentGold
Tristan IsoldeGold
XUANTIEGold
AkeanaSilver
AndesSilver
ArterisSilver
AxeleraSilver
Barcelona Supercomputing Center (BSC-CNS)Silver
Baya SystemsSilver
Chips-ITSilver
CircuitSutraSilver
DeepComputingSilver
ErgtechSilver
GLIWASilver
InfineonSilver
InspireSemiSilver
Lauterbach GMBHSilver
lowRISC C.I.C.Silver
Microchip TechnologySilver
OmniTrustSilver
OpenHW FoundationSilver
PlanVSilver
Pulp PlatformSilver
Real IntentSilver
RIOS labSilver
RiseSilver
Robert Bosch GmbhSilver
SEGGERSilver
SpacemiTSilver
§III

The Programme

Selected from 25 sessions on the bill.
  • TBA

    Accelerating RISC-V Innovation with open MPACT Tools from Google

    The MPACT Tools portfolio provides open-source tools that increase the velocity of HW-SW co-design and development of RISC-V based systems. MPACT-Sim [1] is an ISS framework in C++…

  • TBA

    Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions

    Computational Fluid Dynamics (CFD) relies heavily on the efficiency of linear solvers based on sparse linear algebra kernels. Widely used frameworks like OpenFOAM exploit paralleli…

  • TBA

    All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom

    RISC-V’s Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field λ. This yi…

  • TBA

    An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs

    Driven by the need for zonal control architectures in software-defined vehicles, open-source RISC-V cores are becoming a compelling solution for automotive microprocessor units (MP…

  • TBA

    A Proof-of-Concept RISC-V with 128-bit Extension

    Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a…

  • TBA

    ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V

    Modern data-centric workloads increasingly expose the limitations of traditional von Neumann architectures, where excessive data movement limits throughput and energy efficiency. W…

  • TBA

    A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt

    We present Bianbu LXQt, a user-oriented desktop environment for RISC-V platforms built on a deeply adapted LXQt software stack, optimized for real hardware such as SpacemiT’s K1 an…

  • TBA

    Building the software ecosystem for a RISC-V datacenter

    The RISC-V software ecosystem has grown steadily over the last few years. For embedded software it is reasonably complete, with good compiler, RTOS, and IDE support. The Linux kern…

  • TBA

    CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures

    The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing U…

Intermission
Part the Second · For the Buyer

An audience of 44 companies, parsed from the program.

44 companies in attendance.

The numbers below are derived from the speakers, sponsors, and exhibitors on this page — cross-referenced into one ledger. They are the only thing here that 10times.com cannot tell you.

01Fig. 01 — Composition of the House
0All threespeak · spons · exh
44Sponsoringsponsor only
0Exhibitingexhibitor only
0Speakingspeaker only
03Fig. 03 — The Heaviest in the Room
  1. 01AkeanaSp·S
  2. 02AndesSp·S
  3. 03ArterisSp·S
  4. 04AxeleraSp·S
  5. 05Barcelona Supercomputing Center (BSC-CNS)Sp·S
  6. 06Baya SystemsSp·S
  7. 07Beijing Institute of Open Source ChipSp·P
  8. 08Breker SystemsSp·G
  9. 09CEASp·G
  10. 10Chips-ITSp·S
  11. 11CircuitSutraSp·S
  12. 12DeepComputingSp·S
  13. 13E4 ComputingSp·P
  14. 14EE|TimesSp·M
04Fig. 04 — By Tier
platinum4
9% of 44
gold10
23% of 44
silver27
61% of 44
bronze1
2% of 44
media partner2
5% of 44